The continuous calibration of high-linearity, highspeed analog/digital converters (ADCs) can minimize system complexity by allowing a single converter to maintain its accuracy over time. This paper introduces a continuous calibration technique for pipelined and successive approximation ADCs that avoids some of the limitations of earlier designs by performing the calibration in the analog domain. The calibration is made transparent to the overall system by employing an extra stage that is calibrated outside of the main converter's operation and periodically substituted for a stage within the main converter. A 12-b, pipelined ADC employing this architecture has been integrated in a 0.5-/spl mu/m, single-poly, quadruple-metal, 3.3-V CMOS technology. The measured dynamic performance indicates that at a 10-MHz sampling rate, the circuit achieves a peak signal-to-noise-plus-distortion ratio of 67 dB and a total harmonic distortion of -77 dR for a 4.8-MHz input. The total power dissipated by the prototype is 335 mW, and its active area is 3.71/spl times/3.91 mm/sup 2/.