The Network on-Chip (NoC) is considered as an emerging technology for distributed embedded systems which is proposed as an alternative interconnection solution in Mutli-Processors System on-Chip (MPSoC). This paper proposes a graphical toll that allows researchers to generate and configure quickly their Network on-Chip in the hope to evaluate easily their contributions in no time. Unlike major existing simulators which are developed in hardware language description and make debugging very difficult, this high-level framework helps software designer, who need simpler means, to properly build mapping and scheduler algorithm then validate their contributions. This proposed toll is open source and extensible. The provided conceptual details allow users to efficiently create, validate their real scheduler and mapper as well as integrate it easily.