A low power, high SFDR, ROM-less direct digital frequency synthesizer
H Jafari, A Ayatollahi… - 2005 IEEE Conference on …, 2005 - ieeexplore.ieee.org
This paper describes the design of a ROM-Less Direct Digital Frequency Synthesizer. The
Spurious Free Dynamic Range (SFDR) of the proposed DDFS system is-91.5 ldBc. A DDFS
IC has been designed in HP 0.5 μm standard N-Well CMOS process technology, and that's
layout has 2.489 mm 2 area. A 32-bit frequency control word gives a tuning resolution of
0.023 Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-V supply at
100MHz, and correctly operates up 106MHz.
Spurious Free Dynamic Range (SFDR) of the proposed DDFS system is-91.5 ldBc. A DDFS
IC has been designed in HP 0.5 μm standard N-Well CMOS process technology, and that's
layout has 2.489 mm 2 area. A 32-bit frequency control word gives a tuning resolution of
0.023 Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-V supply at
100MHz, and correctly operates up 106MHz.
[PDF][PDF] A Low Power, High SFDR, Romless Direet Digital Frequeney Synthesizer
A Ayatollahi, H Jafari - IEEE International Frequency Cotrol …, 2006 - academia.edu
This paper describes the design of a ROM-Less Direct Digital Frequency Synthesizer. The
Spurious Free Dynamic Range (SFDR) of the proposed DDFS system is-91.5 ldBc. A DDFS
IC has been designed in HP 0.5 tm standard N-Well CMOS process technology, and that's
layout has 2.489 mm2 area. A 32-bit frequency control word gives a tuning resolution of
0.023 Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-Vsupply at
100MHz, and correctly operates up 106MHz.
Spurious Free Dynamic Range (SFDR) of the proposed DDFS system is-91.5 ldBc. A DDFS
IC has been designed in HP 0.5 tm standard N-Well CMOS process technology, and that's
layout has 2.489 mm2 area. A 32-bit frequency control word gives a tuning resolution of
0.023 Hz at 100MHz sampling rate. This DDFS consume 60mW with 3.3-Vsupply at
100MHz, and correctly operates up 106MHz.
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