A low-power pairing-based cryptographic accelerator for embedded security applications
T English, M Keller, KL Man, E Popovici… - 2009 IEEE …, 2009 - ieeexplore.ieee.org
2009 IEEE International SOC Conference (SOCC), 2009•ieeexplore.ieee.org
We report on the implementation of an IP core for Pairing-based cryptography. The core
performs an elliptic curve cryptographic operation called the Tate Pairing over the field GF (2
251). In this paper, we describe the implementation of the design in TSMC 65 nm GP CMOS
standard cells and the optimisations made for low-power operation. The resulting core
computes the pairing in 1.5 ms and consumes less than 4 mW.
performs an elliptic curve cryptographic operation called the Tate Pairing over the field GF (2
251). In this paper, we describe the implementation of the design in TSMC 65 nm GP CMOS
standard cells and the optimisations made for low-power operation. The resulting core
computes the pairing in 1.5 ms and consumes less than 4 mW.
We report on the implementation of an IP core for Pairing-based cryptography. The core performs an elliptic curve cryptographic operation called the Tate Pairing over the field GF(2 251 ). In this paper, we describe the implementation of the design in TSMC 65 nm GP CMOS standard cells and the optimisations made for low-power operation. The resulting core computes the pairing in 1.5 ms and consumes less than 4 mW.
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