A miniature Q-band CMOS LNA with quadruple-cascode topology
HC Yeh, H Wang - 2011 IEEE MTT-S International Microwave …, 2011 - ieeexplore.ieee.org
HC Yeh, H Wang
2011 IEEE MTT-S International Microwave Symposium, 2011•ieeexplore.ieee.orgIn this paper, a miniature Q-band low noise amplifier (LNA) is fabricated for demonstration
using 90-nm Low Power (LP) CMOS technology. The quadruple-cascode topology is
applied to achieve a high gain performance with a compact chip size. Besides, a transformer
is placed between the cascode devices to reduce the noise figure and enhance the stability
and also bandwidth of the LNA. The LNA features a maximum small signal gain of 20.3 dB
and a minimum noise figure of 4.6 dB at 40 GHz, with a power consumption of 15 mW. The …
using 90-nm Low Power (LP) CMOS technology. The quadruple-cascode topology is
applied to achieve a high gain performance with a compact chip size. Besides, a transformer
is placed between the cascode devices to reduce the noise figure and enhance the stability
and also bandwidth of the LNA. The LNA features a maximum small signal gain of 20.3 dB
and a minimum noise figure of 4.6 dB at 40 GHz, with a power consumption of 15 mW. The …
In this paper, a miniature Q-band low noise amplifier (LNA) is fabricated for demonstration using 90-nm Low Power (LP) CMOS technology. The quadruple-cascode topology is applied to achieve a high gain performance with a compact chip size. Besides, a transformer is placed between the cascode devices to reduce the noise figure and enhance the stability and also bandwidth of the LNA. The LNA features a maximum small signal gain of 20.3 dB and a minimum noise figure of 4.6 dB at 40 GHz, with a power consumption of 15 mW. The chip size is only 0.48 × 0.44 mm 2 , including all the testing pads. To the best of our knowledge, this is the first quadruple-cascode LNA in millimeter-wave (MMW) regime reported to date.
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