A no-verification multi-level-cell (MLC) operation in cross-point OTS-PCM
2020 IEEE Symposium on VLSI Technology, 2020•ieeexplore.ieee.org
We present the first MLC operation for OTS-PCM with comprehensive operation algorithm
study. An ADM chip with fast write speed (< 300ns) and robust operation (> 109 cycles) are
shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell
operation up to 108 cycles without further read verification is achieved based on 100 cells
data from 1Mbit crosspoint array. Systematic discussions of MLC operation under “1/2V”
scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.
study. An ADM chip with fast write speed (< 300ns) and robust operation (> 109 cycles) are
shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell
operation up to 108 cycles without further read verification is achieved based on 100 cells
data from 1Mbit crosspoint array. Systematic discussions of MLC operation under “1/2V”
scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.
We present the first MLC operation for OTS-PCM with comprehensive operation algorithm study. An ADM chip with fast write speed (<300ns) and robust operation (>109 cycles) are shown indicating the potential for high performance MLC OTS-PCM. A desirable 2-bits/cell operation up to 108 cycles without further read verification is achieved based on 100 cells data from 1Mbit crosspoint array. Systematic discussions of MLC operation under “1/2V” scheme is further presented, and threshold voltage (Vt) drift is evaluated accordingly.
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