A novel balanced ternary adder using recharged semi-floating gate devices
H Gundersen, Y Berg - … on Multiple-Valued Logic (ISMVL'06), 2006 - ieeexplore.ieee.org
36th International Symposium on Multiple-Valued Logic (ISMVL'06), 2006•ieeexplore.ieee.org
This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with
Recharged Semi-Floating Gate Devices. By using balanced ternary notation, it possible to
take advantage of carry free addition, which is exploited in designing a fast adder cell. The
circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is
simulated by using Cadence R Analog Design Environment, with CMOS090 process
parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 …
Recharged Semi-Floating Gate Devices. By using balanced ternary notation, it possible to
take advantage of carry free addition, which is exploited in designing a fast adder cell. The
circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is
simulated by using Cadence R Analog Design Environment, with CMOS090 process
parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 …
This paper presents a novel voltage mode Balanced Ternary Adder (BTA), implemented with Recharged Semi- Floating Gate Devices. By using balanced ternary notation, it possible to take advantage of carry free addition, which is exploited in designing a fast adder cell. The circuit operates at 1 GHz clock frequency. The supply voltage is only 1.0 Volt. The circuit is simulated by using Cadence R Analog Design Environment, with CMOS090 process parameters, a 90nm General Purpose Bulk CMOS Process from STMicroelectronics with 7 metal layers. All the capacitors are metal plate capacitors, based on vertical coupling capacitance between stacked metal plates.
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