A single-chip dual-band tri-mode CMOS transceiver for IEEE 802.11 a/b/g wireless LAN
M Zargari, M Terrovitis, SHM Jen… - IEEE Journal of Solid …, 2004 - ieeexplore.ieee.org
M Zargari, M Terrovitis, SHM Jen, BJ Kaczynski, ML Lee, MP Mack, SS Mehta, S Mendis…
IEEE Journal of Solid-State Circuits, 2004•ieeexplore.ieee.orgA single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-
end for an IEEE 802.11 a/b/g wireless LAN is described. The chip is implemented in a 0.25-
/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC
transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM
OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase
noise is-105 dBc/Hz at a 10-kHz offset and the spurs are below-64 dBc when measured at …
end for an IEEE 802.11 a/b/g wireless LAN is described. The chip is implemented in a 0.25-
/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC
transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM
OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase
noise is-105 dBc/Hz at a 10-kHz offset and the spurs are below-64 dBc when measured at …
A single-chip dual-band tri-mode CMOS transceiver that implements the RF and analog front-end for an IEEE 802.11a/b/g wireless LAN is described. The chip is implemented in a 0.25-/spl mu/m CMOS technology and occupies a total silicon area of 23 mm/sup 2/. The IC transmits 9 dBm/8 dBm error vector magnitude (EVM)-compliant output power for a 64-QAM OFDM signal. The overall receiver noise figure is 5.5/4.5 dB at 5 GHz/2.4 GHz. The phase noise is -105 dBc/Hz at a 10-kHz offset and the spurs are below -64 dBc when measured at the 5-GHz transmitter output.
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