Memory performance has become the major bottleneck to improve the overall performance
of the computer system. By using memory controller, there is effective control of data
between processor and memory. In this paper, a memory controller for interfacing
Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random
Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically
Erasable Programmable Read-Only Memory is designed and a coverage driven Constraint …

The major bottleneck of the computer system to improve the overall performance, is the
memory performance. An effective control of data between processor and memory can be
done using memory controller. Verification plays a vital role in any design flow as it is
completed before silicon development. In this work a memory controller for interfacing
Synchronous Static Random Access Memory (SSRAM), Synchronous Dynamic Random
Access Memory (SDRAM), Read Only Memory (ROM) and FLASH which is Electrically …