Most recent timing resilient templates are using asynchronous design techniques and integrating both flip-flops and latches in their design to enable more aggressive performance improvement and reduction in energy consumption. Despite these benefits, they impose challenges in terms of testability because both latches and flip-flops typically use different test protocols. This paper presents an optimized scan cell for flip-flops which is compatible with the protocol used by scannable latches. By using the proposed cell, it is possible to have latches and flip-flops in the same scan chain and the DfT flow fully automated by commercial EDA tools. Experimental results show that the proposed cell reduces silicon area, leakage, and dynamic power compared to the original cell.