Currently, the power consumption is one of the major concerns in VLSI circuit design based on CMOS (Complementary Metal Oxide Semiconductor) and CNTFET (Carbon Nano Tube Field Effect Transistors). As integration and scaling continue to improve and operating frequencies are steadily increased, power utilisation has become a top priority. Circuits and architectures that waste power are dissuaded from use in portable gadgets. The price of an IC’s and system’s packaging is directly proportional to its power dissipation. This paper provides a comprehensive overview of low power VLSI design methodologies for CMOS and CNTFET based circuits, as well as a variety of power dissipation sources.