An efficient method of error correction in fault-tolerant modular neurocomputers
In this paper, we propose the architecture of a fault-tolerant unit in a modular neurocomputer
that is based on decoding with computation of errors syndromes on redundant moduli and
implemented using FPGA and a finite ring neural network. The computational complexity of
the proposed architecture is about 80% less in comparison with that of the architecture
based on number projections in the mixed radix number system.
that is based on decoding with computation of errors syndromes on redundant moduli and
implemented using FPGA and a finite ring neural network. The computational complexity of
the proposed architecture is about 80% less in comparison with that of the architecture
based on number projections in the mixed radix number system.
[引用][C] " An efficient method of error correction in fault tolerant modular neurocomputers", Neurocomputing
NI Chervyakov, PA Lyakhov, MG Babenko… - 2016
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