Analysis and design of 1 GHz PLL for fast phase and frequency acquisition
International Journal of Signal and Imaging Systems Engineering, 2014•inderscienceonline.com
Phase locked loop (PLL) being a mixed signal circuit involves design challenges at high
frequencies. In this work a mixed signal PLL for faster phase and frequency locking is
designed. The PLL is designed and synthesized using GPDK090 library of CMOS 90 nm
process in CADENCE Virtuoso Analog Design Environment for an operating frequency of 1
GHz. Its locking time is 280.6 ns and observed to consume a power of 11.9 mW with a 1.8 V
supply voltage. The complete layout of the PLL is drawn in CADENCE Virtuoso XL and its …
frequencies. In this work a mixed signal PLL for faster phase and frequency locking is
designed. The PLL is designed and synthesized using GPDK090 library of CMOS 90 nm
process in CADENCE Virtuoso Analog Design Environment for an operating frequency of 1
GHz. Its locking time is 280.6 ns and observed to consume a power of 11.9 mW with a 1.8 V
supply voltage. The complete layout of the PLL is drawn in CADENCE Virtuoso XL and its …
Phase locked loop (PLL) being a mixed signal circuit involves design challenges at high frequencies. In this work a mixed signal PLL for faster phase and frequency locking is designed. The PLL is designed and synthesized using GPDK090 library of CMOS 90 nm process in CADENCE Virtuoso Analog Design Environment for an operating frequency of 1 GHz. Its locking time is 280.6 ns and observed to consume a power of 11.9 mW with a 1.8 V supply voltage. The complete layout of the PLL is drawn in CADENCE Virtuoso XL and its behaviour and performance is observed in Spectre.
Inderscience Online