Analysis of a novel non-volatile look-up table (NV LUT) controller design with resistive random-access memories (RRAM) for field-programmable gate arrays (FPGA)
2019 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 2019•ieeexplore.ieee.org
This paper studies the simulation results of a novel controller circuit design for non-volatile
(NV) look-up tables (LUT) combined with an electrical model of a resistive random-access
memory (RRAM)-an emerging non-volatile memory (NVM) device. The Write and Read
schemes of the controller is tested for a 2x2 RRAM array. The selected RRAM successfully
switches between low0'and high1'while the unselected the RRAM remain undisturbed,
demonstrating the elimination of the intrinsic sneak-path current problem in RRAMs …
(NV) look-up tables (LUT) combined with an electrical model of a resistive random-access
memory (RRAM)-an emerging non-volatile memory (NVM) device. The Write and Read
schemes of the controller is tested for a 2x2 RRAM array. The selected RRAM successfully
switches between low0'and high1'while the unselected the RRAM remain undisturbed,
demonstrating the elimination of the intrinsic sneak-path current problem in RRAMs …
This paper studies the simulation results of a novel controller circuit design for non-volatile (NV) look-up tables (LUT) combined with an electrical model of a resistive random-access memory (RRAM)-an emerging non-volatile memory (NVM) device. The Write and Read schemes of the controller is tested for a 2x2 RRAM array. The selected RRAM successfully switches between low `0' and high `1' while the unselected the RRAM remain undisturbed, demonstrating the elimination of the intrinsic sneak-path current problem in RRAMs. Reading of a selected RRAM is also performed with agreeable results.
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