Bulk disambiguation of speculative threads in multiprocessors

L Ceze, J Tuck, J Torrellas, C Cascaval - ACM SIGARCH Computer …, 2006 - dl.acm.org
ACM SIGARCH Computer Architecture News, 2006dl.acm.org
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed
multiprocessors are three popular architectural techniques based on the execution of
multiple, cooperating speculative threads. In these environments, correctly maintaining data
dependences across threads requires mechanisms for disambiguating addresses across
threads, invalidating stale cache state, and making committed state visible. These
mechanisms are both conceptually involved and hard to implement. In this paper, we …
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperating speculative threads. In these environments, correctly maintaining data dependences across threads requires mechanisms for disambiguating addresses across threads, invalidating stale cache state, and making committed state visible. These mechanisms are both conceptually involved and hard to implement. In this paper, we present Bulk, a novel approach to simplify these mechanisms. The idea is to hash-encode a thread's access information in a concise signature, and then support in hardware signature operations that efficiently process sets of addresses. Such operations implement the mechanisms described. Bulk operations are inexact but correct, and provide substantial conceptual and implementation simplicity. We evaluate Bulk in the context of TLS using SPECint2000 codes and TM using multithreaded Java workloads. Despite its simplicity, Bulk has competitive performance with more complex schemes. We also find that signature configuration is a key design parameter.
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