CMOS dynamic comparators for pipeline A/D converters
L Sumanen, M Waltari, V Hakkarainen… - … on Circuits and …, 2002 - ieeexplore.ieee.org
L Sumanen, M Waltari, V Hakkarainen, K Halonen
2002 IEEE International Symposium on Circuits and Systems …, 2002•ieeexplore.ieee.orgThree different CMOS dynamic comparator topologies for pipeline A/D converters, resistive
divider, differential pair, and charge distribution comparators, are analyzed. The topologies
considered are fully differential, ie both sensing and reference voltage inputs are balanced,
consist only of a single stage, and feature zero DC power dissipation with a built-in threshold
adjusting input stage. Test structures of the comparators, fabricated in 0.35-/spl mu/m CMOS
process, are measured to determine the offset properties of the compared topologies.
divider, differential pair, and charge distribution comparators, are analyzed. The topologies
considered are fully differential, ie both sensing and reference voltage inputs are balanced,
consist only of a single stage, and feature zero DC power dissipation with a built-in threshold
adjusting input stage. Test structures of the comparators, fabricated in 0.35-/spl mu/m CMOS
process, are measured to determine the offset properties of the compared topologies.
Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive divider, differential pair, and charge distribution comparators, are analyzed. The topologies considered are fully differential, i.e. both sensing and reference voltage inputs are balanced, consist only of a single stage, and feature zero DC power dissipation with a built-in threshold adjusting input stage. Test structures of the comparators, fabricated in 0.35-/spl mu/m CMOS process, are measured to determine the offset properties of the compared topologies.
ieeexplore.ieee.org
以上显示的是最相近的搜索结果。 查看全部搜索结果