A review of 3-dimensional wafer level stacked backside illuminated CMOS image sensor process technologies

SG Wuu, HL Chen, HC Chien, P Enquist… - … on Electron Devices, 2022 - ieeexplore.ieee.org
… from partitioned logic and sensor array wafers built in separate … The smaller, recessed
dielectric surface area between the … dielectric bond with surface deflection at opposed dielectric

Implementation of HfSiON gate dielectric for sub-60nm DRAM dual gate oxide with recess channel array transistor (RCAT) and tungsten gate

SG Park, BJ Jin, HL Lee, HB Park… - IEDM Technical …, 2004 - ieeexplore.ieee.org
… HfSiON gate dielectric is integrated for the first time in dual gate oxide of DRAM with recess
channel … The cross-sectional TEM image and the gate stack structure of recess channel array

Impact of dielectric and copper via design on wafer-to-wafer hybrid bonding

V Dubey, D Wünsch, K Gottfried… - 2023 IEEE 73rd …, 2023 - ieeexplore.ieee.org
… Some of the latest technologies developed with hybrid bonding technology are image
dielectric shows a slope of less than 1 nm/μm. For 3 μm via arrays, the topography recess is …

Backside illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensors

A Lahav, A Fenigstein, A Strum, S Rizzolo - … Performance Silicon Imaging, 2020 - Elsevier
… This angled light travels through the thick inter-dielectric layer and it may be collected by a …
pixel array and four levels of metals in the array periphery. In addition to the recessed backend…

Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology

E Beyne, SW Kim, L Peng, N Heylen… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
… It has also recently been adopted for high-end CMOS image sensor applications owing to …
minimal dielectric erosion around bonding pad arrays and with the correct protruding or recess

Total dose evaluation of deep submicron CMOS imaging technology through elementary device and pixel array behavior analysis

V Goiffon, P Magnan, O Saint-Pé… - … on Nuclear Science, 2008 - ieeexplore.ieee.org
… first focus on shallow trench isolations, inter layer dielectrics (ILD) and gate oxides using thick
… photodiodes with recessed field oxides. We chose to use a large recess distance, about 5 …

Impact of Dielectric Types on Surface Topography for Wafer-Level Hybrid Bonding

V Dubey, D Wünsch, K Gottfried… - 2024 IEEE 10th …, 2024 - ieeexplore.ieee.org
… is recessed below the dielectric surface, whereas a 'protrusion' occurs when the copper via
surface is elevated above the dielectricarrays with pixel-level optics array and CMOS image

MEMS tunable Fabry-Perot filters with thick, two sided optical coatings

PA Stupar, RL Borwick, JF DeNatale… - … Solid-State Sensors …, 2009 - ieeexplore.ieee.org
… The Adaptive Focal Plane Array (AFPA) is a new spectral imaging technology integrating an
… of the thick dielectric coatings. The silicon is then etched using DRIE to recess the dielectric

Adding New Capabilities to Silicon CMOS Integrated Circuits via Deterministic Assembly

J Kim, T Morrow, L Lin, C Keating, J Mayer… - ECS …, 2011 - iopscience.iop.org
… The top dielectric coating is 300 nm thick. The second … and a dielectric coating patterned
with an array of recessed wells … Figure 3b shows a dark field optical microscope image taken …

Full recess integration of small diameter low threshold VCSELs within Si-CMOS ICs

JM Perkins, TL Simpkins, C Warde, CG Fonstad - Optics Express, 2008 - opg.optica.org
… applications and for a variety of sensor needs. For the most … bottom of recesses etched into
the dielectric stack covering a … 3 array of VCSEL pills bonded in recesses on a CMOS chip …