Challenges and future directions for the scaling of dynamic random-access memory (DRAM)

JA Mandelman, RH Dennard… - IBM Journal of …, 2002 - ieeexplore.ieee.org
JA Mandelman, RH Dennard, GB Bronner, JK DeBrosse, R Divakaruni, Y Li, CJ Radens
IBM Journal of Research and Development, 2002ieeexplore.ieee.org
Significant challenges face DRAM scaling toward and beyond the 0.10-µm generation.
Scaling techniques used in earlier generations for the array-access transistor and the
storage capacitor are encountering limitations which necessitate major innovation in
electrical operating mode, structure, and processing. Although a variety of options exist for
advancing the technology, such as low-voltage operation, vertical MOSFETs, and novel
capacitor structures, uncertainties exist about which way to proceed. This paper discusses …
Significant challenges face DRAM scaling toward and beyond the 0.10-µm generation. Scaling techniques used in earlier generations for the array-access transistor and the storage capacitor are encountering limitations which necessitate major innovation in electrical operating mode, structure, and processing. Although a variety of options exist for advancing the technology, such as low-voltage operation, vertical MOSFETs, and novel capacitor structures, uncertainties exist about which way to proceed. This paper discusses the interrelationships among the DRAM scaling requirements and their possible solutions. The emphasis is on trench-capacitor DRAM technology.
ieeexplore.ieee.org
以上显示的是最相近的搜索结果。 查看全部搜索结果