Over the past decade, many notable achievements on individual single walled carbon nanotube (SWNT) electronic devices have been made. The electrical performances of these SWNT devices even exceed Si-based counterparts in comparable sizes.[1–6] However, practical applications of SWNTs are still facing many daunting challenges. Lack of reliable techniques to define the specific chirality, diameter and orientation of each SWNT significantly degrades the reproducibility of the devices based on individual SWNTs. In contrast, the devices based on SWNT networks (SWNT-NETs) are immune to this problem.[7–11] A random SWNT-NET exhibits superior homogeneous electronic properties due to the involvement of many SWNTs in electrical transport. A SWNT-NET structure can offer 1) attractive statistical physical properties that minimize device-to-device variations, 2) large active areas and high current outputs, and 3) relative insensitivity to the spatial position, etc. In addition, SWNT network can facilitate flexible electronics at a low fabrication cost,[7] etc. It is considered as a promising material to replace amorphous silicon and poly-silicon for electronic applications.[12] For complicated electronic applications, high performance p-type and n-type SWNT field effect transistors (SWNT-FETs) must be employed. With the p-and n-type SWNT-FETs, various low power consumption logic gates and circuits can be constructed. SWNT-FETs are typically p-type in air due to a less hole energy barriers at the SWNT/Au contacts and/or hole doping arising from oxygen adsorption.[13, 14] N-type SWNT-FETs have been fabricated through several different techniques, including chemical doping with K,[15, 16] annealing in vacuum,[14, 16] coating with a low molecular weight polyethyleneimine,[9] utilizing low work function metal contacts, such as Ca,[17] Sc,[5] Y,[18] etc. However, none of these techniques can be immediately applied to achieve n-type SWNT network FETs (SWNT-NET-FETs) for large scale applications. The chemical doping methods are incompatible with conventional silicon processes and the effective n-channel mobility resulted are generally smaller than that of un-doped counterparts. The low work function metal tuning method, an efficient way to achieve n-type FETs for large diameter (large than 1.5 nm) individual SWNTs, is inefficient to change the conduction type of SWNT-NET-FETs in which small diameter SWNTs are also involved. The IBM group firstly demonstrated that a n-type SWNT-FET could be prepared by simply capping PMMA (or a 10 nm thick SiO 2 layer) on a p-type SWNT-FET and then annealing them together in vacuum.[16] Through partial exposure of a SWNT to air, the first complementary logic gate was formed on the SWNT using a common backgate. For SWNT-NET-FETs, there have been only a few demonstrations of complementary logic circuits with a common back-gated structure.[7, 19–23] To our knowledge, all reported logic gates/circuits based on top-gated SWNT-NET-FETs are constructed with unipolar p-type NET-FETs. Those gates/circuits obviously lack the merit of the lowest standing power consumption, which could be offered by complementary structures where p-and n-type FETs are directly involved. In this paper, we have demonstrated an efficient p-to-n conversion of SWNT-NET-FETs using the process of dielectric layer deposition, ie, vacuum annealing followed by Si 3N 4 passivation.[24] Both n-and p-type SWNT-NET-FETs can be achieved through two different dielectric passivaiton materials, ie, Si 3N 4 for n-type and Al 2O 3 for p-type. The n-type devices exhibit slightly better performance than their p-type …