In a delay locked loop (DLL) of a semiconductor memory device capable of compensating
for delay of an internal clock signal by variation of driving strength of an output driver, a
replica output driver exhibits the same delay amount as the delay amount as an output driver
whose driving strength varies. A phase detector detects a phase difference between an
internal clock signal which is delayed by the replica output driver, and an external clock
signal. A control circuit generates a control signal in response to the output signal of the …