DyPhase: A dynamic phase change memory architecture with symmetric write latency and restorable endurance
IG Thakkar, S Pasricha - IEEE Transactions on Computer-Aided …, 2017 - ieeexplore.ieee.org
A major challenge for the widespread adoption of phase change memory (PCM) as main
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation
(ie, an operation that writes “1”) is 2-5 times longer than the latency of a RESET operation
(ie, an operation that writes “0”). For this reason, the average write latency of a PCM system
is limited by the high-latency SET operations. This paper presents a novel PCM architecture
called DyPhase, which uses partial-SET operations instead of the conventional SET …
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation
(ie, an operation that writes “1”) is 2-5 times longer than the latency of a RESET operation
(ie, an operation that writes “0”). For this reason, the average write latency of a PCM system
is limited by the high-latency SET operations. This paper presents a novel PCM architecture
called DyPhase, which uses partial-SET operations instead of the conventional SET …
DyPhase: A dynamic phase change memory architecture with symmetric write latency
IG Thakkar, S Pasricha - … Conference on VLSI Design and 2017 …, 2017 - ieeexplore.ieee.org
A major challenge for the widespread adoption of phase change memory (PCM) as main
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation
(ie, an operation that writes'1') is 2-5 times longer than the latency of a RESET operation (ie,
an operation that writes'0'). For this reason, the average write latency of a PCM system is
limited by the high-latency SET operations. This paper presents a novel PCM architecture
called DyPhase, which uses partial-SET operations instead of the conventional SET …
memory is its asymmetric write latency. Generally, for a PCM, the latency of a SET operation
(ie, an operation that writes'1') is 2-5 times longer than the latency of a RESET operation (ie,
an operation that writes'0'). For this reason, the average write latency of a PCM system is
limited by the high-latency SET operations. This paper presents a novel PCM architecture
called DyPhase, which uses partial-SET operations instead of the conventional SET …
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