ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm
2023 IEEE Symposium on VLSI Technology and Circuits (VLSI …, 2023•ieeexplore.ieee.org
A multi-level (2 bits/bitcell) SRAM PUF is introduced to uniquely enable ECC-less operation
with PUF capacity exceeding storage capacity at no cell modification. The first PUF bit is
generated from steady-state post-reset bitcell value with> 4X higher stability than
conventional power-up. The second is simultaneously extracted from the transient response.
Above-storage capacity and improved stability eliminate ECC down to the SRAM
V_min(0.6V) at 75-fJ/bit energy and 3.3% area overhead in 28 nm.
with PUF capacity exceeding storage capacity at no cell modification. The first PUF bit is
generated from steady-state post-reset bitcell value with> 4X higher stability than
conventional power-up. The second is simultaneously extracted from the transient response.
Above-storage capacity and improved stability eliminate ECC down to the SRAM
V_min(0.6V) at 75-fJ/bit energy and 3.3% area overhead in 28 nm.
A multi-level (2 bits/bitcell) SRAM PUF is introduced to uniquely enable ECC-less operation with PUF capacity exceeding storage capacity at no cell modification. The first PUF bit is generated from steady-state post-reset bitcell value with > 4X higher stability than conventional power-up. The second is simultaneously extracted from the transient response. Above-storage capacity and improved stability eliminate ECC down to the SRAM at 75-fJ/bit energy and 3.3% area overhead in 28 nm.
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