Efficient FPGA-based reconfigurable accelerators for SIMON cryptographic algorithm on embedded platforms

A Alkamil, DG Perera - 2019 International Conference on …, 2019 - ieeexplore.ieee.org
2019 International Conference on ReConFigurable Computing and …, 2019ieeexplore.ieee.org
With the advancement of embedded computing, many applications are becoming common
on these devices, which have stringent constraints and requirements. FPGA-based systems
are currently the most promising avenue to support applications on embedded platforms.
Furthermore, it is imperative to ensure the security of the applications running on these
highly constrained embedded devices. In this paper, we introduce novel, unique, and
efficient FPGA-based reconfigurable accelerators (both hardware and software) for the …
With the advancement of embedded computing, many applications are becoming common on these devices, which have stringent constraints and requirements. FPGA-based systems are currently the most promising avenue to support applications on embedded platforms. Furthermore, it is imperative to ensure the security of the applications running on these highly constrained embedded devices. In this paper, we introduce novel, unique, and efficient FPGA-based reconfigurable accelerators (both hardware and software) for the SIMON lightweight cryptographic algorithm on embedded devices, considering the associated constraints and requirements. Both our hardware and software designs are generic, parameterized, and scalable; thus, without changing the internal architectures, our designs can be reconfigured on-the-fly: to perform either the encryption or the decryption; and to process varying block sizes and varying key sizes. Our embedded designs are highly flexible and reconfigurable, hence can be utilized for various applications with diverse security requirements. We also introduce the system-level architecture for our FPGA-based hardware/software SIMON designs, with unique techniques to overcome memory limitations and memory access latency. Experiments are performed to evaluate the feasibility and efficiency of our proposed accelerators on embedded platforms. Our reconfigurable hardware designs achieve 59 times speedup compared to its software counterparts.
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