Efficient and effective placement for very large circuits
WJ Sun, C Sechen - … on Computer-Aided Design of Integrated …, 1995 - ieeexplore.ieee.org
WJ Sun, C Sechen
IEEE Transactions on Computer-Aided Design of Integrated Circuits …, 1995•ieeexplore.ieee.orgWe present a new approach to simulated annealing and a new hierarchical algorithm for
row-based placement which has obtained the best results ever reported for a large set of
MCNC benchmark circuits. Our results indicate that chip area reductions up to 15% are
achieved compared with TimberWolfSC v6. 0. Our new hierarchical annealing-based
placement algorithm (TimberWolfSC v7. 0) yields chip area reductions up to 21% while
consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6. 0 …
row-based placement which has obtained the best results ever reported for a large set of
MCNC benchmark circuits. Our results indicate that chip area reductions up to 15% are
achieved compared with TimberWolfSC v6. 0. Our new hierarchical annealing-based
placement algorithm (TimberWolfSC v7. 0) yields chip area reductions up to 21% while
consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6. 0 …
We present a new approach to simulated annealing and a new hierarchical algorithm for row-based placement which has obtained the best results ever reported for a large set of MCNC benchmark circuits. Our results indicate that chip area reductions up to 15% are achieved compared with TimberWolfSC v6.0. Our new hierarchical annealing-based placement algorithm (TimberWolfSC v7.0) yields chip area reductions up to 21% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0. Furthermore, TimberWolfSC v7.0 produces lower total wire length by an average of 8% than Gordian/Domino, 11% lower wire length than Ritual/Tiger, while using comparable run time. TimberWolfSC v7.0 also supports precise timing driven placement.< >
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