Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain …

M Radosavljevic, G Dewey, D Basu… - 2011 international …, 2011 - ieeexplore.ieee.org
M Radosavljevic, G Dewey, D Basu, J Boardman, B Chu-Kung, JM Fastenau, S Kabehie…
2011 international electron devices meeting, 2011ieeexplore.ieee.org
In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect
transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (L
SIDE) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices
demonstrate electrostatics improvement over the ultra-thin (QW thickness, T QW= 10nm)
body planar InGaAs device due to (i) narrow fin width (W FIN) of 30nm and (ii) high quality
high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs …
In this work, 3-D Tri-gate and ultra-thin body planar InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and scaled gate-to-source/gate-to-drain (L SIDE ) have been fabricated and compared. For the first time, 3-D Tri-gate InGaAs devices demonstrate electrostatics improvement over the ultra-thin (QW thickness, T QW =10nm) body planar InGaAs device due to (i) narrow fin width (W FIN ) of 30nm and (ii) high quality high-K gate dielectric interface on the InGaAs fin. Additionally, the 3-D Tri-gate InGaAs devices in this work achieve the best electrostatics, as evidenced by the steepest SS and the smallest DIBL, ever reported for any high-K III-V field effect transistor. The results in this work show that the 3-D Tri-gate device architecture is an effective way to improve the scalability of III-V FETs for future low power logic applications.
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