We consider the balance between compute density and interconnect in Coarse-Grained Reconfigurable Architectures (CGRAs) intended for acceleration of HPC applications. We model a baseline CGRA architecture [2] in the open-source CGRA-ME framework [11] and describe the modelling as a case study. Then, holding the interconnect fabric constant, we create several variants of the baseline CGRA: 1) one having reduced (sparser) compute capability where not all ALUs are fully capable, 2) one having increased (denser) compute capability, where the amount of compute is roughly doubled relative to the baseline, and 3) one with increased I/O bandwidth. In an experimental study, we evaluate all architectures to assess application mappability and resource usage for a set of benchmark applications. We also evaluate silicon area consumption using a standard-cell ASIC flow. Results show the baseline CGRA to be overprovisioned in both compute and interconnect, with the proposed variants offering superior area efficiency.