FPGASort: A high performance sorting architecture exploiting run-time reconfiguration on FPGAs for large problem sorting

D Koch, J Torresen - Proceedings of the 19th ACM/SIGDA international …, 2011 - dl.acm.org
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011dl.acm.org
This paper analyses different hardware sorting architectures in order to implement a highly
scaleable sorter for solving huge problems at high performance up to the GB range in linear
time complexity. It will be proven that a combination of a FIFO-based merge sorter and a tree-
based merge sorter results in the best performance at low cost. Moreover, we will
demonstrate how partial run-time reconfiguration can be used for saving almost half the
FPGA resources or alternatively for improving the speed. Experiments show a sustainable …
This paper analyses different hardware sorting architectures in order to implement a highly scaleable sorter for solving huge problems at high performance up to the GB range in linear time complexity. It will be proven that a combination of a FIFO-based merge sorter and a tree-based merge sorter results in the best performance at low cost. Moreover, we will demonstrate how partial run-time reconfiguration can be used for saving almost half the FPGA resources or alternatively for improving the speed. Experiments show a sustainable sorting throughput of 2GB/s for problems fitting into the on-chip FPGA memory and 1 GB/s when using external memory. These values surpass the best published results on large problem sorting implementations on FPGAs, GPUs, and the Cell processor.
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