Fast addition using balanced ternary counters designed with CMOS semi-floating gate devices
H Gundersen, Y Berg - … on Multiple-Valued Logic (ISMVL'07), 2007 - ieeexplore.ieee.org
37th International Symposium on Multiple-Valued Logic (ISMVL'07), 2007•ieeexplore.ieee.org
This paper presents ternary counters using balanced ternary notation. The balanced ternary
counters can replace binary full adders or counters in fast adder structures. The circuits use
recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it
is possible to build balanced ternary addition circuits, which can add both negative and
positive operands, by using the same adder blocks. The circuit operates at a clock frequency
of 1 Ghz. The supply voltage 1.0 Volt.
counters can replace binary full adders or counters in fast adder structures. The circuits use
recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it
is possible to build balanced ternary addition circuits, which can add both negative and
positive operands, by using the same adder blocks. The circuit operates at a clock frequency
of 1 Ghz. The supply voltage 1.0 Volt.
This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative and positive operands, by using the same adder blocks. The circuit operates at a clock frequency of 1 Ghz. The supply voltage 1.0 Volt.
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