Fast and compact dynamic ripple carry adder design
CJ Fang, CH Huang, JS Wang… - Proceedings. IEEE Asia …, 2002 - ieeexplore.ieee.org
CJ Fang, CH Huang, JS Wang, CW Yeh
Proceedings. IEEE Asia-Pacific Conference on ASIC,, 2002•ieeexplore.ieee.orgAdders are fundamental building blocks and often constitute part of the critical path. In this
paper, we propose four high-speed ripple carry adder designs using dynamic circuit
techniques. CMOS technology based SPICE simulations show that the proposed dynamic
ripple carry adders are at least two times faster than the conventional static ripple carry
adder. Further, all of the proposed designs compare much favorably to a previous dynamic
ripple carry adder design that employs DCVS (differential cascode voltage switch) logic.
paper, we propose four high-speed ripple carry adder designs using dynamic circuit
techniques. CMOS technology based SPICE simulations show that the proposed dynamic
ripple carry adders are at least two times faster than the conventional static ripple carry
adder. Further, all of the proposed designs compare much favorably to a previous dynamic
ripple carry adder design that employs DCVS (differential cascode voltage switch) logic.
Adders are fundamental building blocks and often constitute part of the critical path. In this paper, we propose four high-speed ripple carry adder designs using dynamic circuit techniques. CMOS technology based SPICE simulations show that the proposed dynamic ripple carry adders are at least two times faster than the conventional static ripple carry adder. Further, all of the proposed designs compare much favorably to a previous dynamic ripple carry adder design that employs DCVS (differential cascode voltage switch) logic.
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