… A low-noise fast-lock PLL [1] with adaptive bandwidth control can lock in about 30 clock …
Menoux, “Clock/data recovery PLL using half-frequency clock,” IEEE J. Solid-State Circuits, …

… High jitter tolerance, low clock jitter, and fast lock time have been achieved by careful selection
of phase detection loop parameters. Due to its simple structure, it has the advantages of …

… A low-noise fast-lock PLL with adaptive bandwidth control can lock in about 30 clock cycles
with 20 ps peak-to-peak jitter [23]. However, it uses a reference clock as input instead of …

… The estimation calculated only from the past 10 bit-transition timing enables the fast lock
and higher jitter tracking performance. Experimental results demonstrated that the FPGA based …

… Thus, the proposed PLL has fast-lock, low-jitter, and wide-operating frequency and can be
used in modern high-performance microprocessing system and clock data recovery system. …

… Menoux, “Clock/data recovery PLL using half-frequency clock,” IEEE J. SolidState Circuits, …
Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE J. Solid-…

… Menoux, “Clock/data recovery PLL using half-frequency clock,” IEEE J. SolidState Circuits, …
Kim, “A low-noise fast-lock phase-locked loop with adaptive bandwidth control,” IEEE J. Solid-…

… Kim, "A low-noise fast-lock phase-locked loop with adaptive bandwidth control," IEEE J. …
Ahn, "A 5Gb/s 0.25~m CMOS jitter-tolerant variable-interval oversampling clock/data recovery …

… recovery (CDR) circuits play a critical role for achieving required receiver performance. In …
oversampling transceiver with dead-zone phase detection for robust clock/data recovery,” …

… and Data Recovery (CDR), a key receiver timing circuit in clock-embedded serial link systems,
becomes … A unity-gain buffer for input data and output buffers for recovered clock/data are …