Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction
We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors
to be applicable to designs where the functional units and memories have multicycle and
possibly arbitrary latency. We also show ways to incorporate exceptions and branch
prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted
Functions [4][5]. We study the modeling of the above features in different versions of dual-
issue superscalar processors.
to be applicable to designs where the functional units and memories have multicycle and
possibly arbitrary latency. We also show ways to incorporate exceptions and branch
prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted
Functions [4][5]. We study the modeling of the above features in different versions of dual-
issue superscalar processors.
We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly arbitrary latency. We also show ways to incorporate exceptions and branch prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted Functions [4][5]. We study the modeling of the above features in different versions of dual-issue superscalar processors.
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