One method disclosed herein includes forming an opening in a layer of materialso as to
expose the source/drain regions of a transistor and a first portion of a gate cap layer
positioned above an active region, reducing the thickness of a portion of the gate cap layer
positioned above the isolation region, defin ing separate initial source/drain contacts
positioned on oppo site sides of the gate structure, performing a common etching process
sequence to define agate contact opening that extends through the reduced-thickness …