Fractional-order differentiation and integration stages are essential building blocks for performing signal processing using fractional-order calculus. One important characteristic of fractional-order differentiators/integrators is the circuit complexity of the integer-order topologies required for approximating such stages. The already introduced schemes suffer from this obstacle, making the derived structures power demanding. A simple structure, constructed from 21 MOS transistors and 3 dc current sources, which is capable of approximating fractional-order differentiators and integrators is presented in this paper. Other attractive benefits of the proposed scheme are the electronic tuning capability as well as the capability for implementation in monolithic form. The evaluation of its behavior is performed using Cadence and the Design Kit provided by the Austrian Mikro Systems (AMS) 0.35μm CMOS process.