Gate‐level body biasing technique for high‐speed sub‐threshold CMOS logic gates
International journal of circuit theory and applications, 2014•Wiley Online Library
An efficient technique for designing high‐performance logic circuits operating in sub‐
threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change
dynamically the threshold voltage of transistors on the basis of the gate status. Such an
auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency.
If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate
designed as described here shows a delay reduction between 20%(16%) and 40%(48%) …
threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change
dynamically the threshold voltage of transistors on the basis of the gate status. Such an
auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency.
If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate
designed as described here shows a delay reduction between 20%(16%) and 40%(48%) …
An efficient technique for designing high‐performance logic circuits operating in sub‐threshold region is proposed. A simple gate‐level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency.
If 200 aJ is the target total energy per operation consumption, a two input NAND (NOR) gate designed as described here shows a delay reduction between 20% (16%) and 40% (48%), with respect to previously proposed sub‐threshold approaches. Copyright 2012 John Wiley & Sons, Ltd.
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