As logic devices continue to downscale, interconnections are reaching the nanoscale where quantum effects are important. In this work we introduce a semi-empirical method to describe the resistance of copper interconnections of the sizes predicted by ITRS roadmap. The resistance calculated by our method was benchmarked against DFT for single grain boundaries. We describe a computationally efficient method that matches DFT benchmarks within a few percent. The 1000x speed up compared to DFT allows us to describe grain boundaries with a 30 nm channel length that are too large to be simulated by ab-initio methods. The electrical resistance of these grain boundaries has a probability density distribution as a function of the grain rotation angles. This approach allows us to quantitatively obtain the most likely resistance for each configuration.