Hardware-efficient systolization of DA-based calculation of finite digital convolution
PK Meher - IEEE Transactions on Circuits and Systems II …, 2006 - ieeexplore.ieee.org
IEEE Transactions on Circuits and Systems II: Express Briefs, 2006•ieeexplore.ieee.org
Novel one-and two-dimensional systolic structures are designed for computation of circular
convolution using distributed arithmetic (DA). The proposed structures involve significantly
less memory and less area-delay complexity compared with the existing DA-based
structures for circular convolution. Besides, it is shown that the proposed systolic designs for
circular convolution can be used for computation of linear convolution as well
convolution using distributed arithmetic (DA). The proposed structures involve significantly
less memory and less area-delay complexity compared with the existing DA-based
structures for circular convolution. Besides, it is shown that the proposed systolic designs for
circular convolution can be used for computation of linear convolution as well
Novel one- and two-dimensional systolic structures are designed for computation of circular convolution using distributed arithmetic (DA). The proposed structures involve significantly less memory and less area-delay complexity compared with the existing DA-based structures for circular convolution. Besides, it is shown that the proposed systolic designs for circular convolution can be used for computation of linear convolution as well
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