High performance FET with elevated source/drain region

R Divakaruni, LC Hsu, RV Joshi, CJ Radens - US Patent 6,864,540, 2005 - Google Patents
2. Background Description Typical Semiconductor integrated circuit (IC) design goals
include high performance (circuit Switching frequency) and density (transistors per unit area)
at mini mum circuit power. Semiconductor technology and chip manufacturing advances
have continually reduced circuit feature dimensions and, correspondingly, Supply Voltage to
pack more function in the same area. To minimize power, many ICS are made in the well-
known complementary insulated gate field effect transistor (FET) technology known as …

High performance FET with elevated source/drain region

R Divakaruni, LC Hsu, RV Joshi, CJ Radens - US Patent 7,566,599, 2009 - Google Patents
(57) ABSTRACT A field effect transistor (FET), integrated circuit (IC) chip including the FETs
and a method of forming the FETs. The FETs include a thin channel with raised source/drain
(RSD) regions at each end on an insulator layer, eg, on an ultra-thin silicon on insulator
(SOI) chip. Isolation trenches at each end of the FETs, ie, at the end of the RSD regions,
isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET
gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on …
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