High speed hardware implementation of modified Reed-Solomon decoder
A decoder suitable for use in a digital communications system utilizing an RS (n′, k′) code
modified from an RS (n, k) code receives n′-symbol vectors each including k′ message
symbols and r′= n′− k′ parity symbols and decodes the n′-symbol vectors to correct
errors therein, wherein n, k, n′, and k′ are integers, and k′< n′< n, k′< k< n, and
wherein the decoder stores therein one erasure locator polynomial σ 0 (x). The decoder
includes a syndrome calculator for receiving the n′-symbol vectors and for calculating …
modified from an RS (n, k) code receives n′-symbol vectors each including k′ message
symbols and r′= n′− k′ parity symbols and decodes the n′-symbol vectors to correct
errors therein, wherein n, k, n′, and k′ are integers, and k′< n′< n, k′< k< n, and
wherein the decoder stores therein one erasure locator polynomial σ 0 (x). The decoder
includes a syndrome calculator for receiving the n′-symbol vectors and for calculating …
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