Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and Ion = 10 μA/μm for Ioff = 1 nA/μm at Vds = 0.3 V
E Memisevic, J Svensson… - … IEEE International …, 2016 - ieeexplore.ieee.org
We present a vertical nanowire InAs/GaAsSb/GaSb TFET with a highly scaled InAs diameter
(20 nm). The device exhibits a minimum subthreshold swing of 48 mV/dec. for V ds = 0.1–…
(20 nm). The device exhibits a minimum subthreshold swing of 48 mV/dec. for V ds = 0.1–…
A 7nm CMOS platform technology featuring 4th generation FinFET transistors with a 0.027um2 high density 6-T SRAM cell for mobile SoC applications
SY Wu, CY Lin, MC Chiang, JJ Liaw… - … IEEE International …, 2016 - ieeexplore.ieee.org
For the first time, a leading edge 7nm CMOS platform technology for mobile SoC applications
is presented. This technology provides >3.3X routed gate density and 35%∼40% speed …
is presented. This technology provides >3.3X routed gate density and 35%∼40% speed …
A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell
S Thompson, N Anand, M Armstrong… - … Electron Devices …, 2002 - ieeexplore.ieee.org
… High mobility is achieved by making devices with equivalent fixed oxide charge and surface
roughness compared to bulk. In this work, both the electron and hole mobility gains are …
roughness compared to bulk. In this work, both the electron and hole mobility gains are …
5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and …
G Yeap, SS Lin, YM Chen, HL Shang… - … IEEE International …, 2019 - ieeexplore.ieee.org
A leading edge 5nm CMOS platform technology has been defined and optimized for mobile
and HPC applications. This industry-leading 5nm technology features, for the first time, full-…
and HPC applications. This industry-leading 5nm technology features, for the first time, full-…
Advances in 3D CMOS sequential integration
P Batude, M Vinet, A Pouydebasque… - … IEEE International …, 2009 - ieeexplore.ieee.org
For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub
22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si …
22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si …
A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs
M Trentzsch, S Flachowsky, R Richter… - … IEEE International …, 2016 - ieeexplore.ieee.org
We successfully implemented a one-transistor (1T) ferroelectric field effect transistor (FeFET)
eNVM into a 28nm gate-first super low power (28SLP) CMOS technology platform using …
eNVM into a 28nm gate-first super low power (28SLP) CMOS technology platform using …
A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and …
C Auth, A Aliyarukunju, M Asoro… - … IEEE International …, 2017 - ieeexplore.ieee.org
A 10nm logic technology using 3rd-generation FinFET transistors with Self-Aligned Quad
Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local …
Patterning (SAQP) for critical patterning layers, and cobalt local interconnects at three local …
3nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications
As the most feasible solution beyond FinFET technology, a gate-all-around Multi-Bridge-Channel
MOSFET (MBCFET) technology is successfully demonstrated including a fully working …
MOSFET (MBCFET) technology is successfully demonstrated including a fully working …
High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors
P Packan, S Akbar, M Armstrong… - … international electron …, 2009 - ieeexplore.ieee.org
A 32nm logic technology for high performance microprocessors is described. 2 nd generation
high-k + metal gate transistors provide record drive currents at the tightest gate pitch …
high-k + metal gate transistors provide record drive currents at the tightest gate pitch …
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57/spl mu/m/sup 2/SRAM cell
P Bai, C Auth, S Balakrishnan, M Bost… - … . IEEE International …, 2004 - ieeexplore.ieee.org
A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length,
enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high …
enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high …
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