[HTML][HTML] Impact of optimization on high-k material gate spacer in DG-FinFET device
AF Roslan, F Salehuddin, AS Zain… - Proc Mech Eng Res …, 2019 - books.google.com
AF Roslan, F Salehuddin, AS Zain, KE Kaharudin
Proc Mech Eng Res Day, 2019•books.google.comThis paper investigates the impact of the high-K material gate spacer on short channel
effects (SCEs) for the 16 nm double-gate finFET, with output responses optimized using L9
orthogonal array (OA) Taguchi method. Virtual fabrication process and electrical
characterization is implemented, and significant improvement is shown towards TiO2 and
HfO2 material in terms of the ION/IOFF ratio obtained at 4.0337× 106 and 3.6089× 106 for
0.179±12.7% V of threshold voltage (VTH). The ION from high-K materials has proved to …
effects (SCEs) for the 16 nm double-gate finFET, with output responses optimized using L9
orthogonal array (OA) Taguchi method. Virtual fabrication process and electrical
characterization is implemented, and significant improvement is shown towards TiO2 and
HfO2 material in terms of the ION/IOFF ratio obtained at 4.0337× 106 and 3.6089× 106 for
0.179±12.7% V of threshold voltage (VTH). The ION from high-K materials has proved to …
Abstract
This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs) for the 16 nm double-gate finFET, with output responses optimized using L9 orthogonal array (OA) Taguchi method. Virtual fabrication process and electrical characterization is implemented, and significant improvement is shown towards TiO2 and HfO2 material in terms of the ION/IOFF ratio obtained at 4.0337× 106 and 3.6089× 106 for 0.179±12.7% V of threshold voltage (VTH). The ION from high-K materials has proved to meet the minimum requirement by International Technology Roadmap Semiconductor (ITRS) 2013 for high performance Multi-Gate technology for the year 2015.
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