Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same

T Cho, HJ Kang, HW Shin, GS Byun, SJ Kim - US Patent 7,180,154, 2007 - Google Patents
Integrated circuit memory devices provided on an inte grated circuit Substrate are typically
tested prior to assembly of the memory device. During this process, the integrated circuit
memory devices may be classified as either good or bad. If a chip classified as bad
malfunctions due to one or more failed cells, the failed cell (s) may be replaced by a
redundant cell already included in the memory device. The repair process may include
irradiating a laser-beam used to blow one or more fuses. Blowing the fuse (s) allows the …

Integrated circuit devices having corrosion resistant fuse regions and methods of fabricating the same

T Cho, HJ Kang, HW Shin, GS Byun… - US Patent App. 11 …, 2007 - Google Patents
0001. This application is a divisional application of and claims priority to copending US
patent application Ser. No. 10/845,048, filed May 13, 2004, which claims priority from
Korean Patent Application No. 2003-41249, filed on Jun. 24. 2003, the disclosures of which
are hereby incorporated herein by reference as if set forth in their entirety.
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