In this paper, proposed a new approach to implement a high performance carbon nanotube FET (CNTFET) based nine transistor (9T) SRAM cell. Due to scaling limit, conventional CMOS technology needs to be replaced with highly efficient carbon nanotube (CNT) based transistors. The CNTFET based memory circuit has drastically enhanced performance, like stability, high speed switching and significant reduction in physical layout area. Further, leakage current and standby power dissipation can be minimized by using multi-threshold technology. The dual chirality selection is also important phenomena to improve the performance of SRAM cell or say that the chirality selection can adjust the threshold voltage of transistors. As the threshold voltage, highly affects on the performance of CNTFET device, the operation of SRAM cell with a near subthreshod voltage has significant effects on power dissipation. The presented paper, also compare the conventional 6T SRAM cell, 8T SRAM cell and previous 9T SRAM cell. The proposed 9T SRAM cell has the similar read speed, but the write speed improved by 1.77× as compared to previous 9T SRAM cell. The physical layout of new 9T SRAM decreases by 4.9% as compared to previous 9T SRAM cell, but this increases 1.87× as compared to conventional 6T SRAM. The leakage power consumption for the proposed 9T SRAM cell have also considerable reductions compared to 6T, 8T and previous 9T SRAM cell by 4.8×, 3.6× and 3.1×, respectively. The energy dissipations evaluated for 1 Kbit consumes 118.9 fJ for the supply voltage V DD of 0.325 V, near subthreshold region, found minimum for the proposed 9T SRAM cell.