This paper addresses the power issues faced by dynamic comparator for small input
differential voltage. In this paper analysis for delay and power consumption of dynamic
comparator is presented. Based on theoretical equations, an activity factor is reduced in
order to consume least power. By removing cross coupled inverter pair and employing
different node discharge method a design of a dynamic comparator with low transistor count
is presented. The reduction in activity factor of nodes gives promising minimization in power …

This paper introduces the design of dynamic voltage comparator with reduced activity factor
for low voltage and low power operation. An analysis of CMOS circuit power consumption is
presented along with implication of activity factor on power consumption. A new architecture
based on theoretical analysis for a dynamic comparator is proposed. The proposed
comparator has a reduced activity factor and thus it consumes less power and it also has
reduced transistor count over the design of double tail dynamic comparator which gives the …