polysilicon gate were fabricated with self-aligned process and characterized. Polysilicon and
dopant activation processes were optimized such that leakage current and equivalent oxide
thickness (EOT) of HfO/sub 2/remain low (EOT of 12.0/spl Aring/. HfO/sub 2/with 1/spl
times/10/sup-3/A/cm/sup 2/at Vg= 1.0 V). Reasonable N-and P-MOSFET characteristics such
as subthreshold swing of 74 mV/decade and output currents were also demonstrated.