Master-slave level shifter array architecture with pre-defined power-up states
Primary Examiner—Jung Kim (74) Attorney, Agent, or Firm—Haynes and Boone, LLP (57)
ABSTRACT A master-slave level shifter array includes an asymmetric master level shifter
having a predefined output state that produces an enable signal to drive an array of
symmetric slave level shifters during a power collapse. As a result, the slave level shifter
array has a reliable output state during a power collapse, while also providing wafer area
savings due to their small symmetric characteristics. 10 Claims, 4 Drawing Sheets
ABSTRACT A master-slave level shifter array includes an asymmetric master level shifter
having a predefined output state that produces an enable signal to drive an array of
symmetric slave level shifters during a power collapse. As a result, the slave level shifter
array has a reliable output state during a power collapse, while also providing wafer area
savings due to their small symmetric characteristics. 10 Claims, 4 Drawing Sheets
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