A multipage cell architecture for high-speed programming multilevel NAND flash memories

K Takeuchi, T Tanaka… - IEEE Journal of Solid-State …, 1998 - ieeexplore.ieee.org
… In NAND flash memories, the cell read current is as small as 1 A. Therefore, the read access
time is determined by the bitline capacitance, and the delay time of the wordline boosting …

Multipage Read for nand Flash

T Luo, B Peleato - IEEE Transactions on Circuits and Systems II …, 2016 - ieeexplore.ieee.org
read method, which we call multipage read, that can help alleviate some of the challenges
that the flash … method can be applied to improve several applications of flash memories as we …

NAND flash memory with multiple page sizes for high-performance storage devices

JY Kim, SH Park, H Seo, KW Song… - … Transactions on Very …, 2015 - ieeexplore.ieee.org
… A unit of NFM's read and program … a multiple-page-size NFM architecture and its
management. Our method dramatically improves write performance through adopting multiple page

FastRead: Improving read performance for multilevel-cell flash memory

DW Chang, WC Lin, HH Chen - IEEE Transactions on Very …, 2016 - ieeexplore.ieee.org
… , each cell corresponds to a specific bit for multiple pages. For example, in Fig. 1(a), each …
the read-latency difference among pages to improve the read performance of MLC NAND flash

Performance and Lifetime Optimizations for Large-Capacity NAND Storage Systems

박지성 - 2019 - s-space.snu.ac.kr
… Secondly, we propose a new read operation for large-page NAND flash memory, called …
reasons, NAND flash memory performs erase operations on a group of multiple pages, called a …

Fspda: A full sequence program data allocation scheme for boosting 3d nand flash read performance

S Pang, Y Deng, Z Wu, G Zhang, J Li… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
… Full sequence program or FSP can program multiple pages in a word line at a time, thereby
improving write throughput. Unfortunately, large-grained FSP operations coarsely aggregate …

Subpage programming for extending the lifetime of NAND flash memory

JH Kim, SH Kim, JS Kim - 2015 Design, Automation & Test in …, 2015 - ieeexplore.ieee.org
… needs to be written to NAND flash memory, we should read corresponding page, update a
… Those cells which share the same W/L form a page and multiple pages compose an erase …

μ*-Tree: An ordered index structure for NAND flash memory with adaptive page layout scheme

JS Ahn, D Kang, D Jung, JS Kim… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
… or to a multiple page size for NAND flash memory.There are … NAND flash memory simulator
which performs raw flash read… latency of MLC NAND flash memory: 165:6 s for read, 905:8 s …

A page padding method for fragmented flash storage

H Kim, JH Kim, SH Choi, HR Jung, JG Jung - Computational Science and …, 2007 - Springer
… It consists of multiple blocks, a block consists of multiple pages, and a page … In a NAND
flash memory, the read / write operation unit is a page. That is, we can read and write NAND flash

An adaptive double area page replacement algorithm for nand flash

J Li, H Hu - Journal of Physics: Conference Series, 2021 - iopscience.iop.org
NAND read and write operations are based on pages, and erase operations are based on
blocks. Flash … When writing back to flash memory, multiple pages are written back at once. …