This paper presents a method for optimizing void-free copper filling of through-silicon vias (TSVs) through the interaction of additives and current density for applications in 3D integrated circuits such as those used in dynamic random access memory (DRAM) and complementary metal-oxide semiconductor (CMOS) image sensors.

Studies of through-silicon vias (TSVs) have become important owing to the increasing demand for 3D packaging. To obtain high-performance devices, it is important to fill the holes inside TSVs without voids. In this study, poly(ethylene glycol), bis-(3-sodiumsulfopropyl disulfide), and Janus Green B are used as a suppressor, accelerator, and leveler, respectively, to achieve void-free filling of a TSV. The optimum conditions for the additives were studied, and electrochemical analysis was performed to confirm their effects. Different current conditions, such as pulse, pulse-reverse, and periodic pulse-reverse, were also employed to enhance the filling properties of copper (Cu) for a TSV with a hole diameter of 60 µm and depth/hole aspect ratios of 2, 2.5, and 3. The behavior of Cu filling was observed through a cross-sectional analysis of the TSV after Cu plating under various conditions.