… its small cell area advantage. In a high resistive load memory cell, the memory cell area can
… CMOS six-transistor memory cell, which consists of two PMOS transistors and four NMOS …

… a PMOSNMOS-PMOS (PNP) type cell which we fabricated as a reference is shown. The PND
cell … gate non-volatile memory cell and the operation mechanism of this PND cell. Since we …

… produce a memory cell with the same size 6-T cell that … PMOS to the 6-T cell and 4-T cell
reduces the cell size. To achieve our target cell size, we applied a vertical PMOS to a 4-T cell. …

… Fig.la shows the memory cell equivalent circuit where the double-gated PMOS TFT loads …
After bulk CMOS transistors fabrication the TFT loads (Q5, Q6) are formed on the memory cell …

… where N is the number of memory cells per chip, M is the number of memory cells per word
line, and tcycle is the operating cycle time. The condition for charging the highstorage node …

… be a pMOS transistor [3]–[7], but the erase efficiency of the cell is low as pMOS transistor has
… The coupling device can also be a pMOS transistor [3]–[9] or nMOS transistor [10]–[13], and …

… Gate 2 is a pseudo-pMOS NAND gate; we use these … Our memory cells are configured
as an addressable array with no … Finally, our cells can be designed to use either an nFET-injector …

… data movement between logic and memory chips [1]. 2T gain cell memory (also called 2T0C
… candidate to fulfill this requirement as a memory cell contains only two transistors, write and …

… indicate that the SSTFT is good enough for the load PMOS transistor of the SRAM cell. … The
load PMOS SSTFT for the novel 3-0 S’ SRAM cell is successfully developed. The load PMOS …

… our purpose of the evaluation for PMOS memory cell. The fundamental memory circuit
architecture is illustrated in Fig. 13. The memory cell array is divided to two regions, one is the left …