In recent years, there has been a shift towards increasing parallelism and heterogeneity in processor design [96, 97]. As traditional uniprocessors hit the clock speed, power, instructionlevel parallelism and complexity walls, chip designers have been forced to rethink computer architecture from the ground up. This has led to an explosion in new architectures such as graphics processing units (GPUs), digital signal processors (DSP) and field-programmable gate arrays (FPGA). Additionally, general-purpose CPUs have been re-architected in order to meet energy and performance goals for varying form factors [50, 26]. It is clear that emerging computer systems will be increasingly heterogeneous in order to achieve better energy efficiency and higher performance.

Recently there has been a tremendous amount of change in CPU microarchitecture in order to reach different power and performance targets. With the advent of smartphones, CPU designers have built processors that strike a balance between low power and reasonable performance [50, 20]. The high-performance computing (HPC) community has embraced heterogeneity, with the top two supercomputers in the Top500 list [100] mixing symmetric chip-multiprocessors (CMP) with general-purpose and OS-capable [70] many-core accelerators. Additionally, the HPC community has begun to include energy efficiency as a primary design goal as they realized they could not continue scaling the number of cores at current power consumption levels [31]. Chip designers have even begun to include heterogeneous CPU cores together on a single die in order to achieve high performance and energy efficiency for a variety of workloads [46, 68].