Positive bias temperature instability in nMOSFETs with ultra-thin Hf-silicate gate dielectrics
Positive bias temperature instability (PBTI) in nMOSFETs with ultra thin HfSiON gate
dielectrics has been investigated. We propose that PBTI is due to electron trapping in the
high-k dielectrics layer and we present results of measurements performed at different bias
condition and temperatures consistent with the proposed model. Extrapolated lifetimes
indicate that PBTI in HfSiON gate dielectrics severely impacts the reliability of CMOS devices
only in the case of Hf rich-layers.
dielectrics has been investigated. We propose that PBTI is due to electron trapping in the
high-k dielectrics layer and we present results of measurements performed at different bias
condition and temperatures consistent with the proposed model. Extrapolated lifetimes
indicate that PBTI in HfSiON gate dielectrics severely impacts the reliability of CMOS devices
only in the case of Hf rich-layers.
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